Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

7-52 Vol. 3A
MULTIPLE-PROCESSOR MANAGEMENT
7.11.6.1 Use the PAUSE Instruction in Spin-Wait Loops
Intel recommends that a PAUSE instruction be placed in all spin-wait loops that run on
Intel processors supporting Hyper-Threading Technology and multi-core processors.
Software routines that use spin-wait loops include multiprocessor synchronization
primitives (spin-locks, semaphores, and mutex variables) and idle loops. Such
routines keep the processor core busy executing a load-compare-branch loop while a
thread waits for a resource to become available. Including a PAUSE instruction in such
a loop greatly improves efficiency (see Section 7.11.2, “PAUSE Instruction”). The
following routine gives an example of a spin-wait loop that uses a PAUSE instruction:
Spin_Lock:
CMP lockvar, 0 ;Check if lock is free
JE Get_Lock
PAUSE ;Short delay
JMP Spin_Lock
Get_Lock:
MOV EAX, 1
XCHG EAX, lockvar ;Try to get lock
CMP EAX, 0 ;Test if successful
JNE Spin_Lock
Critical_Section:
<critical section code>
MOV lockvar, 0
...
Continue:
The spin-wait loop above uses a “test, test-and-set” technique for determining the
availability of the synchronization variable. This technique is recommended when
writing spin-wait loops.
In IA-32 processor generations earlier than the Pentium 4 processor, the PAUSE
instruction is treated as a NOP instruction.
7.11.6.2 Potential Usage of MONITOR/MWAIT in C0 Idle Loops
An operating system may implement different handlers for different idle states. A
typical OS idle loop on an ACPI-compatible OS is shown in Example 7-5:
Example 7-5. A Typical OS Idle Loop
// WorkQueue is a memory location indicating there is a thread
// ready to run. A non-zero value for WorkQueue is assumed to
// indicate the presence of work to be scheduled on the processor.
// The idle loop is entered with interrupts disabled.
WHILE (1) {