Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

7-54 Vol. 3A
MULTIPLE-PROCESSOR MANAGEMENT
MWAIT
}
}
}
}
// C1 handler uses a Halt instruction.
VOID C1Handler()
{STI
HLT
}
7.11.6.3 Halt Idle Logical Processors
If one of two logical processors is idle or in a spin-wait loop of long duration, explicitly
halt that processor by means of a HLT instruction.
In an MP system, operating systems can place idle processors into a loop that contin-
uously checks the run queue for runnable software tasks. Logical processors that
execute idle loops consume a significant amount of core’s execution resources that
might otherwise be used by the other logical processors in the physical package. For
this reason, halting idle logical processors optimizes the performance.
1
If all logical
processors within a physical package are halted, the processor will enter a power-
saving state.
7.11.6.4 Potential Usage of MONITOR/MWAIT in C1 Idle Loops
An operating system may also consider replacing HLT with MONITOR/MWAIT in its C1
idle loop. An example is shown in Example 7-7:
Example 7-7. An OS Idle Loop with MONITOR/MWAIT in the C1 Idle Loop
// WorkQueue is a memory location indicating there is a thread
// ready to run. A non-zero value for WorkQueue is assumed to
// indicate the presence of work to be scheduled on the processor.
// The following example assumes that the necessary padding has been
// added surrounding WorkQueue to eliminate false wakeups
// The idle loop is entered with interrupts disabled.
WHILE (1) {
IF (WorkQueue) THEN {
// Schedule work at WorkQueue
1. Excessive transitions into and out of the HALT state could also incur performance penalties.
Operating systems should evaluate the performance trade-offs for their operating system.