Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A xxxiii
CONTENTS
PAGE
Table 15-2. Software Interrupt Handling Methods While in Virtual-8086 Mode . . . . . . . . . . . 15-26
Table 16-1. Characteristics of 16-Bit and 32-Bit Program Modules . . . . . . . . . . . . . . . . . . . . . . . . .16-1
Table 17-1. New Instruction in the Pentium Processor and Later IA-32 Processors . . . . . . . . .17-5
Table 17-2. Recommended Values of the EM, MP, and NE Flags for Intel486 SX
Microprocessor/Intel 487 SX Math Coprocessor System . . . . . . . . . . . . . . . . . . . . . 17-22
Table 17-3. EM and MP Flag Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-22
Table 18-1. Breakpoint Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-7
Table 18-2. Debug Exception Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-9
Table 18-3. LBR MSR Stack Structure for the Pentium
®
4 and the
Intel
®
Xeon
®
Processor Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-19
Table 18-4. MSR_DEBUGCTLA, IA32_DEBUGCTL, MSR_DEBUGCLTB Flag Encodings . . . . . . . 18-28
Table 18-5. CPL-Qualified Branch Trace Store Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-29
Table 18-6. UMask and Event Select Encodings for Pre-Defined Architectural
Performance Events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-43
Table 18-7. Core Specificity Encoding within a Non-Architectural Umask . . . . . . . . . . . . . . . . . 18-46
Table 18-8. Agent Specificity Encoding within a Non-Architectural Umask. . . . . . . . . . . . . . . . 18-46
Table 18-9. HW Prefetch Qualification Encoding within a Non-Architectural Umask . . . . . . . 18-46
Table 18-10. MESI Qualification Definitions within a Non-Architectural Umask . . . . . . . . . . . . . 18-47
Table 18-12. Snoop Type Qualification Definitions within a Non-Architectural Umask . . . . . . 18-48
Table 18-11. Bus Snoop Qualification Definitions within a Non-Architectural Umask. . . . . . . . 18-48
Table 18-13. Association of Fixed-Function Performance Counters with Architectural
Performance Events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-49
Table 18-14. At-Retirement Performance Events for Intel Core Microarchitecture . . . . . . . . . 18-52
Table 18-15. PEBS Performance Events for Intel Core Microarchitecture . . . . . . . . . . . . . . . . . . 18-52
Table 18-16. Requirements to Program PEBS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-54
Table 18-17. Performance Counter MSRs and Associated CCCR and ESCR MSRs
(Pentium 4 and Intel Xeon Processors) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-56
Table 18-18. Event Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-71
Table 18-19. CCR Names and Bit Positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-77
Table 18-20. Effect of Logical Processor and CPL Qualification for Logical-
Processor-Specific (TS) Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-90
Table 18-21. Effect of Logical Processor and CPL Qualification for Non-logical-
Processor-specific (TI) Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-90
Table 20-1. Format of the VMCS Region. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-2
Table 20-2. Format of Access Rights . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-4
Table 20-3. Format of Interruptibility State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-6
Table 20-4. Format of Pending-Debug-Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-8
Table 20-5. Definitions of Pin-Based VM-Execution Controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-9
Table 20-6. Definitions of Processor-Based VM-Execution Controls . . . . . . . . . . . . . . . . . . . . . . 20-10
Table 20-7. Definitions of VM-Exit Controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-15
Table 20-8. Format of an MSR Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-16
Table 20-9. Definitions of VM-Entry Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-17
Table 20-10. Format of the VM-Entry Interruption-Information Field . . . . . . . . . . . . . . . . . . . . . . 20-18
Table 20-11. Format of Exit Reason . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-19
Table 20-12. Format of the VM-Exit Interruption-Information Field. . . . . . . . . . . . . . . . . . . . . . . . 20-20
Table 20-13. Format of the IDT-Vectoring Information Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-21
Table 20-14. Format of the VMX-Instruction Information Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-22
Table 20-15. Structure of VMCS Component Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-25
Table 23-1. Exit Qualification for Debug Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-5
Table 23-2. Exit Qualification for Task Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-6
Table 23-3. Exit Qualification for Control-Register Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-7
Table 23-4. Exit Qualification for MOV DR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-8