Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

8-4 Vol. 3A
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
Both the local APIC and the I/O APIC are designed to operate in MP systems (see
Figures 8-2 and 8-3). Each local APIC handles interrupts from the I/O APIC, IPIs from
processors on the system bus, and self-generated interrupts. Interrupts can also be
delivered to the individual processors through the local interrupt pins; however, this
mechanism is commonly not used in MP systems.
Figure 8-2. Local APICs and I/O APIC When Intel Xeon Processors Are Used in
Multiple-Processor Systems
Figure 8-3. Local APICs and I/O APIC When P6 Family Processors Are Used in
Multiple-Processor Systems
I/O APIC
External
Interrupts
System Chip Set
Processor System Bus
CPU
Local APIC
Processor #2
CPU
Local APIC
Processor #3
CPU
Local APIC
Processor #1
CPU
Local APIC
Processor #3
Bridge
PCI
IPIs IPIs IPIs
Interrupt
Messages
IPIs
Interrupt
Messages
Interrupt
Messages
Interrupt
Messages
Interrupt
Messages
CPU
Local APIC
P
rocessor
#2
CPU
Local APIC
P
rocessor
#3
CPU
Local APIC
P
rocessor
#1
Interrupt
Messages
I/O APIC
External
Interrupts
System Chip Set
3-wire APIC Bus
CPU
Local APIC
P
rocessor
#4
IPIs
IPIs
IPIs
IPIs
Interrupt
Messages
Interrupt
Messages
Interrupt
Messages
Interrupt
Messages