Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

CONTENTS
xxxiv Vol. 3A
PAGE
Table 23-5. Exit Qualification for I/O Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-8
Table 24-1. SMRAM State Save Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-6
Table 24-2. ISMRAM State Save Map for Intel 64 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-8
Table 24-3. Processor Register Initialization in SMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-12
Table 24-4. I/O Instruction Information in the SMM State Save Map . . . . . . . . . . . . . . . . . . . . . . 24-15
Table 24-5. I/O Instruction Type Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-16
Table 24-6. Auto HALT Restart Flag Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-19
Table 24-7. I/O Instruction Restart Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24-21
Table 24-1. Exit Qualification for SMIs That Arrive Immediately After the
Retirement of an I/O Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-27
Table 24-1. Format of MSEG Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-32
Table 25-1. Operating Modes for Host and Guest Environments . . . . . . . . . . . . . . . . . . . . . . . . . .25-14
Table A-1. Architectural Performance Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2
Table A-2. Fixed-Function Performance Counter and Pre-defined Performance Events . . . . . A-3
Table A-3. Non-Architectural Performance Events in Processors Based on
Intel Core Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-4
Table A-4. Non-Architectural Performance Events in Intel Core Solo and
Intel Core Duo Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-46
Table A-5. Performance Monitoring Events Supported by Intel NetBurst
Microarchitecture for Non-Retirement Counting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-56
Table A-6. Performance Monitoring Events For Intel NetBurst Microarchitecture
for At-Retirement Counting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-86
Table A-7. Intel NetBurst Microarchitecture Model-Specific Performance Monitoring
Events (For Model Encoding 3, 4 or 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-93
Table A-9. List of Metrics Available for Execution Tagging (For Execution Event Only). . . . . A-94
Table A-8. List of Metrics Available for Front_end Tagging (For Front_end Event Only). . . . A-94
Table A-10. List of Metrics Available for Replay Tagging (For Replay Event Only). . . . . . . . . . . A-95
Table A-11. Event Mask Qualification for Logical Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-97
Table A-12. Performance Monitoring Events on Intel
®
Pentium
®
M Processors . . . . . . . . . . .A-103
Table A-13. Performance Monitoring Events Modified on Intel
®
Pentium
®
M Processors . .A-104
Table A-14. Events That Can Be Counted with the P6 Family Performance-
Monitoring Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-106
Table A-15. Events That Can Be Counted with Pentium Processor
Performance-Monitoring Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-123
Table B-1. MSRs in Processors Based on Intel Core Microarchitecture . . . . . . . . . . . . . . . . . . . . . B-1
Table B-2. MSRs in the Pentium 4 and Intel Xeon Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-21
Table B-3. MSRs Unique to 64-bit Intel Xeon Processor MP with Up to an
8 MB L3 Cache. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-64
Table B-4. MSRs in Intel Core Solo, Intel Core Duo Processors, and Dual-core Intel
Xeon Processor LV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-65
Table B-5. MSRs in Pentium M Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-82
Table B-6. MSRs in the P6 Family Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-92
Table B-7. MSRs in the Pentium Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-103
Table B-8. IA-32 Architectural MSRs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-104
Table C-1. Boot Phase IPI Message Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .C-2
Table E-1. Incremental Decoding Information: Processor Family 06H Machine Error
Codes For Machine Check. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .E-1
Table E-2. Incremental Decoding Information: Processor Family 0FH Machine Error
Codes For Machine Check. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .E-5
Table E-3. Decoding Family 0FH Machine Check Codes for Memory Hierarchy Errors . . . . . . . .E-7
Table F-1. EOI Message (14 Cycles). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .F-1
Table F-2. Short Message (21 Cycles) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .F-2