Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

8-16 Vol. 3A
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
• LVT LINT1 Register (FEE0 0360H) — Specifies interrupt delivery when an
interrupt is signaled at the LINT1 pin.
• LVT Error Register (FEE0 0370H) — Specifies interrupt delivery when the
APIC detects an internal error (see Section 8.5.3, “Error Handling”).
The LVT performance counter register and its associated interrupt were introduced in
the P6 processors and are also present in the Pentium 4 and Intel Xeon processors.
The LVT thermal monitor register and its associated interrupt were introduced in the
Pentium 4 and Intel Xeon processors.
As shown in Figures 8-8, some of these fields and flags are not available (and
reserved) for some entries.