Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

8-32 Vol. 3A
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
MDA are compared with bits 28 through 31 of the LDR to determine if a local APIC
is part of the cluster. Bits 24 through 27 of the MDA are compared with Bits 24
through 27 of the LDR to identify a local APICs within the cluster.
Sets of processors within a cluster can be specified by writing the target cluster
address in bits 28 through 31 of the MDA and setting selected bits in bits 24
through 27 of the MDA, corresponding to the chosen members of the cluster. In
this mode, 15 clusters (with cluster addresses of 0 through 14) each having 4
local APICs can be specified in the message. For the P6 and Pentium processor’s
local APICs, however, the APIC arbitration ID supports only 15 APIC agents.
Therefore, the total number of processors and their local APICs supported in
this mode is limited to 15. Broadcast to all local APICs is achieved by setting all
destination bits to one. This guarantees a match on all clusters and selects all
APICs in each cluster. A broadcast IPI or I/O subsystem broadcast interrupt with
lowest priority delivery mode is not supported in cluster mode and must not be
configured by software.
The hierarchical cluster destination model can be used with Pentium 4, Intel
Xeon, P6 family, or Pentium processors. With this model, a hierarchical network
can be created by connecting different flat clusters via independent system or
APIC buses. This scheme requires a cluster manager within each cluster, which is
responsible for handling message passing between system or APIC buses. One
cluster contains up to 4 agents. Thus 15 cluster managers, each with 4 agents,
can form a network of up to 60 APIC agents. Note that hierarchical APIC networks
requires a special cluster manager device, which is not part of the local or the I/O
APIC units.
NOTES
All processors that have their APIC software enabled (using the
spurious vector enable/disable bit) must have their DFRs (Desti-
nation Format Registers) programmed identically.
The default mode for DFR is flat mode. If you are using cluster mode,
DFRs must be programmed before the APIC is software enabled.
Since some chipsets do not accurately track a system view of the
logical mode, program DFRs as soon as possible after starting the
processor.
8.6.2.3 Broadcast/Self Delivery Mode
The destination shorthand field of the ICR allows the delivery mode to be by-passed
in favor of broadcasting the IPI to all the processors on the system bus and/or back
to itself (see Section 8.6.1, “Interrupt Command Register (ICR)”). Three destination
shorthands are supported: self, all excluding self, and all including self. The destina-
tion mode is ignored when a destination shorthand is used.