Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 8-33
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
8.6.2.4 Lowest Priority Delivery Mode
With lowest priority delivery mode, the ICR is programmed to send an IPI to several
processors on the system bus, using the logical or shorthand destination mechanism
for selecting the processor. The selected processors then arbitrate with one another
over the system bus or the APIC bus, with the lowest-priority processor accepting the
IPI.
For systems based on the Intel Xeon processor, the chipset bus controller accepts
messages from the I/O APIC agents in the system and directs interrupts to the
processors on the system bus. When using the lowest priority delivery mode, the
chipset chooses a target processor to receive the interrupt out of the set of possible
targets. The Pentium 4 processor provides a special bus cycle on the system bus that
informs the chipset of the current task priority for each logical processor in the
system. The chipset saves this information and uses it to choose the lowest priority
processor when an interrupt is received.
For systems based on P6 family processors, the processor priority used in lowest-
priority arbitration is contained in the arbitration priority register (APR) in each local
APIC. Figure 8-15 shows the layout of the APR.
The APR value is computed as follows:
IF (TPR[7:4]
≥ IRRV[7:4]) AND (TPR[7:4] > ISRV[7:4])
THEN
APR[7:0]
← TPR[7:0]
ELSE
APR[7:4]
← max(TPR[7:4] AND ISRV[7:4], IRRV[7:4])
APR[3:0]
← 0.
Here, the TPR value is the task priority value in the TPR (see Figure 8-18), the IRRV
value is the vector number for the highest priority bit that is set in the IRR (see
Figure 8-20) or 00H (if no IRR bit is set), and the ISRV value is the vector number for
the highest priority bit that is set in the ISR (see Figure 8-20). Following arbitration
among the destination processors, the processor with the lowest value in its APR
handles the IPI and the other processors ignore it.
(P6 family and Pentium processors.) For these processors, if a focus processor
exists, it may accept the interrupt, regardless of its priority. A processor is said to be
Figure 8-15. Arbitration Priority Register (APR)
31 078
Reserved
Address: FEE0 0090H
Value after reset: 0H
Arbitration Priority Sub-Class
Arbitration Priority
43