Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

8-42 Vol. 3A

ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)

bit is cleared for edge-triggered interrupts and set for level-triggered interrupts. If a

TMR bit is set when an EOI cycle for its corresponding interrupt vector is generated,

an EOI message is sent to all I/O APICs.

8.8.5 Signaling Interrupt Servicing Completion

For all interrupts except those delivered with the NMI, SMI, INIT, ExtINT, the start-

up, or INIT-Deassert delivery mode, the interrupt handler must include a write to the

end-of-interrupt (EOI) register (see Figure 8-21). This write must occur at the end of

the handler routine, sometime before the IRET instruction. This action indicates that

the servicing of the current interrupt is complete and the local APIC can issue the

next interrupt from the ISR.

Upon receiving and EOI, the APIC clears the highest priority bit in the ISR and

dispatches the next highest priority interrupt to the processor. If the terminated

interrupt was a level-triggered interrupt, the local APIC also sends an end-of-inter-

rupt message to all I/O APICs.

For future compatibility, the software is requested to issue the end-of-interrupt

command by writing a value of 0H into the EOI register.

8.8.6 Task Priority in IA-32e Mode

In IA-32e mode, operating systems can manage the 16 priority classes of external

interrupts (see Section 8.8.3, “Interrupt, Task, and Processor Priority”) explicitly

using the task priority register (TPR). Operating systems can use the TPR to tempo-

rarily block specific (low-priority) interrupts from interrupting a high-priority task.

This is done by loading TPR with a value corresponding to the highest-priority inter-

rupt that is to be blocked. For example:

• Loading the TPR with a value of 8 (01000B) blocks all interrupts with a priority of

8 or less while allowing all interrupts with a priority of nine or more to be

recognized.

• Loading the TPR with zero enables all external interrupts.

• Loading the TPR with 0F (01111B) disables all external interrupts.

Figure 8-21. EOI Register

Address: 0FEE0 00B0H

Value after reset: 0H