Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 1-3
ABOUT THIS MANUAL
Chapter 4 — Protection. Describes the support for page and segment protection
provided in the Intel 64 and IA-32 architectures. This chapter also explains the
implementation of privilege rules, stack switching, pointer validation, user and
supervisor modes.
Chapter 5 — Interrupt and Exception Handling. Describes the basic interrupt
mechanisms defined in the Intel 64 and IA-32 architectures, shows how interrupts
and exceptions relate to protection, and describes how the architecture handles each
exception type. Reference information for each exception is given at the end of this
chapter.
Chapter 6 — Task Management. Describes mechanisms the IA-32 architecture
provides to support multitasking and inter-task protection.
Chapter 7 — Multiple-Processor Management. Describes the instructions and
flags that support multiple processors with shared memory, memory ordering, and
Hyper-Threading Technology.
Chapter 8 — Advanced Programmable Interrupt Controller (APIC). Describes
the programming interface to the local APIC and gives an overview of the interface
between the local APIC and the I/O APIC.
Chapter 9 — Processor Management and Initialization. Defines the state of an
Intel 64 or IA-32 processor after reset initialization. This chapter also explains how to
set up an Intel 64 or IA-32 processor for real-address mode operation and protected-
mode operation, and how to switch between modes.
Chapter 10 — Memory Cache Control. Describes the general concept of caching
and the caching mechanisms supported by the Intel 64 or IA-32 architectures. This
chapter also describes the memory type range registers (MTRRs) and how they can
be used to map memory types of physical memory. Information on using the new
cache control and memory streaming instructions introduced with the Pentium III,
Pentium 4, and Intel Xeon processors is also given.
Chapter 11 — Intel
®
MMX™ Technology System Programming. Describes
those aspects of the Intel
®
MMX™ technology that must be handled and considered
at the system programming level, including: task switching, exception handling, and
compatibility with existing system environments.
Chapter 12 — System Programming for Streaming SIMD Instruction Sets.
Describes those aspects of SSE/SSE2/SSE3 extensions that must be handled and
considered at the system programming level, including task switching, exception
handling, and compatibility with existing system environments.
Chapter 13 — Power and Thermal Management. Describes the architecture’s
power and the thermal monitoring facilities.
Chapter 14 — Machine-Check Architecture. Describes the machine-check archi-
tecture.
Chapter 15 — 8086 Emulation. Describes the real-address and virtual-8086
modes of the IA-32 architecture.