Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

1-4 Vol. 3A
ABOUT THIS MANUAL
Chapter 16 — Mixing 16-Bit and 32-Bit Code. Describes how to mix 16-bit and
32-bit code modules within the same program or task.
Chapter 17 — IA-32 Architecture Compatibility. Describes architectural
compatibility among IA-32 processors.
Chapter 18 — Debugging and Performance Monitoring. Describes the debug-
ging registers and other debug mechanism provided in Intel 64 or IA-32 processors.
This chapter also describes the time-stamp counter and the performance-monitoring
counters.
Chapter 19 — Introduction to Virtual-Machine Extensions. Describes the basic
elements of virtual machine architecture and the virtual-machine extensions for
Intel 64 and IA-32 Architectures.
Chapter 20 — Virtual-Machine Control Structures. Describes components that
manage VMX operation. These include the working-VMCS pointer and the control-
ling-VMCS pointer.
Chapter 21— VMX Non-Root Operation. Describes the operation of a VMX non-
root operation. Processor operation in VMX non-root mode can be restricted
programmatically such that certain operations, events or conditions can cause the
processor to transfer control from the guest (running in VMX non-root mode) to the
monitor software (running in VMX root mode).
Chapter 22 — VM Entries. Describes VM entries. VM entry transitions the processor
from the VMM running in VMX root-mode to a VM running in VMX non-root mode.
VM-Entry is performed by the execution of VMLAUNCH or VMRESUME instructions.
Chapter 23 — VM Exits. Describes VM exits. Certain events, operations or situa-
tions while the processor is in VMX non-root operation may cause VM-exit transitions.
In addition, VM exits can also occur on failed VM entries.
Chapter 24 — System Management. Describes Intel 64 and IA-32 architectures’
system management mode (SMM) facilities.
Chapter 25 — Virtual-Machine Monitoring Programming Considerations.
Describes programming considerations for VMMs. VMMs manage virtual machines
(VMs).
Chapter 26 — Virtualization of System Resources. Describes the virtualization
of the system resources. These include: debugging facilities, address translation,
physical memory, and microcode update facilities.
Chapter 27 — Handling Boundary Conditions in a Virtual Machine Monitor.
Describes what a VMM must consider when handling exceptions, interrupts, error
conditions, and transitions between activity states.
Appendix A — Performance-Monitoring Events. Lists the events that can be
counted with the performance-monitoring counters and the codes used to select
these events. Both Pentium processor and P6 family processor events are described.
Appendix B — Model-Specific Registers (MSRs). Lists the MSRs available in the
Pentium processors, the P6 family processors, the Pentium 4, Intel Xeon, Intel Core