Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

9-46 Vol. 3A
PROCESSOR MANAGEMENT AND INITIALIZATION
Example 9-8. Assembly Code Example of Simple Microcode Update Loader
mov ecx,79h ; MSR to read in ECX
xor eax,eax ; clear EAX
xor ebx,ebx ; clear EBX
mov ax,cs ; Segment of microcode update
shl eax,4
mov bx,offset Update ; Offset of microcode update
add eax,ebx ; Linear Address of Update in EAX
add eax,48d ; Offset of the Update Data within the Update
xor edx,edx ; Zero in EDX
WRMSR ; microcode update trigger
The loader shown in Example 9-8 assumes that update is the address of a microcode
update (header and data) embedded within the code segment of the BIOS. It also
assumes that the processor is operating in real mode. The data may reside anywhere
in memory, aligned on a 16-byte boundary, that is accessible by the processor within
its current operating mode (real, protected).
Before the BIOS executes the microcode update trigger (WRMSR) instruction, the
following must be true:
• EAX contains the linear address of the start of the update data
• EDX contains zero
• ECX contains 79H (address of IA32_BIOS_UPDT_TRIG)
Other requirements are:
• If the update is loaded while the processor is in real mode, then the update data
may not cross a segment boundary.
• If the update is loaded while the processor is in real mode, then the update data
may not exceed a segment limit.
• If paging is enabled, pages that are currently present must map the update data.
• The microcode update data requires a 16-byte boundary alignment.
9.11.6.1 Hard Resets in Update Loading
The effects of a loaded update are cleared from the processor upon a hard reset.
Therefore, each time a hard reset is asserted during the BIOS POST, the update must
be reloaded on all processors that observed the reset. The effects of a loaded update
are, however, maintained across a processor INIT. There are no side effects caused
by loading an update into a processor multiple times.
9.11.6.2 Update in a Multiprocessor System
A multiprocessor (MP) system requires loading each processor with update data
appropriate for its CPUID and platform ID bits. The BIOS is responsible for ensuring
that this requirement is met and that the loader is located in a module executed by