Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 10-3
MEMORY CACHE CONTROL
Intel 64 and IA-32 processors may implement four types of caches: the trace cache,
the level 1 (L1) cache, the level 2 (L2) cache, and the level 3 (L3) cache. See
Figure 10-1. Cache availability is described below:
• Intel Core 2 processor and Intel Xeon processor 5100 Series— The L1
cache is divided into two sections: one section is dedicated to caching instruc-
tions (pre-decoded instructions) and the other caches data. The L2 cache is a
unified data and instruction cache is located on the processor chip; it is shared
between two processor cores in a dual-core processor implementation. No trace
cache is implemented.
• Intel Core Solo and Intel Core Duo processors — The L1 cache is divided into
two sections: one section is dedicated to caching instructions (pre-decoded
instructions) and the other caches data. The L2 cache is a unified data and
instruction cache located on the processor chip. It is shared between two
processor cores in a dual-core processor implementation. No trace cache is
implemented.
• Pentium 4 and Intel Xeon processors — The trace cache caches decoded
instructions (μops) from the instruction decoder and the L1 cache contains data.
Instruction TLB
(Large Pages)
- Intel Core 2 Duo processors: 4 entries, 4 ways.
- Pentium 4 and Intel Xeon processors: large pages are fragmented.
- Intel Core Duo, Intel Core Solo, Pentium M processor: 2 entries, fully
associative.
- P6 family processors: 2 entries, fully associative.
- Pentium processor: Uses same TLB as used for 4-KByte pages.
Data TLB (Large
Pages)
- Intel Core 2 Duo processors: DTLB0, 16 entries, DTLB1, 32 entries, 4 ways.
- Pentium 4 and Intel Xeon processors: 64 entries, fully set associative; shared
with small page data TLBs.
- Intel Core Duo, Intel Core Solo, Pentium M processor: 8 entries, fully
associative.
- P6 family processors: 8 entries, 4-way set associative.
- Pentium processor: 8 entries, 4-way set associative; uses same TLB as used for
4-KByte pages in Pentium processors with MMX technology.
Store Buffer
- Intel Core 2 Duo processors: 20 entries.
- Pentium 4 and Intel Xeon processors: 24 entries.
- Pentium M processor: 16 entries.
- P6 family processors: 12 entries.
- Pentium processor: 2 buffers, 1 entry each (Pentium processors with MMX
technology have 4 buffers for 4 entries).
Write Combining
(WC) Buffer
- Intel Core 2 Duo processors: 8 entries.
- Pentium 4 and Intel Xeon processors: 6 or 8 entries.
- Intel Core Duo, Intel Core Solo, Pentium M processors: 6 entries.
- P6 family processors: 4 entries.
NOTES:
1 Introduced to the IA-32 architecture in the Pentium 4 and Intel Xeon processors.
Table 10-1. Characteristics of the Caches, TLBs, Store Buffer, and
Write Combining Buffer in Intel 64 and IA-32 Processors (Contd.)
Cache or Buffer Characteristics