Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

10-20 Vol. 3A
MEMORY CACHE CONTROL
10.5.2.2 Selecting Memory Types for Pentium III and More Recent
Processor Families
The Intel Core 2 Duo, Intel Core Duo, Intel Core Solo, Pentium M, Pentium 4, Intel
Xeon, and Pentium III processors use the PAT to select effective page-level memory
types. Here, a memory type for a page is selected by the MTRRs and the value in a
PAT entry that is selected with the PAT, PCD and PWT bits in a page-table or page-
directory entry (see Section 10.12.3, “Selecting a Memory Type from the PAT”). Table
10-7 describes the mapping of MTRR memory types and PAT entry types to effective
memory types, when normal caching is in effect (the CD and NW flags in control
register CR0 are clear). The combinations shown in gray are implementation-defined
for the Pentium 4, Intel Xeon, and Pentium III processors. System designers are
encouraged to avoid the implementation-defined combinations.
Table 10-7. Effective Page-Level Memory Types for Pentium III and More Recent
Processor Families
MTRR Memory Type PAT Entry Value Effective Memory Type
UC UC UC
1
UC- UC
1
WC WC
WT UC
1
WB UC
1
WP UC
1
WC UC UC
2
UC- WC
WC WC
WT UC
2,3
WB WC
WP UC
2,3
WT UC UC
2
UC- UC
2
WC WC
WT WT
WB WT
WP WP
3