Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

10-22 Vol. 3A
MEMORY CACHE CONTROL
10.5.3 Preventing Caching
To disable the L1, L2, and L3 caches after they have been enabled and have received
cache fills, perform the following steps:
1. Enter the no-fill cache mode. (Set the CD flag in control register CR0 to 1 and
the NW flag to 0.
2. Flush all caches using the WBINVD instruction.
3. Disable the MTRRs and set the default memory type to uncached or set all MTRRs
for the uncached memory type (see the discussion of the discussion of the TYPE
field and the E flag in Section 10.11.2.1, “IA32_MTRR_DEF_TYPE MSR”).
The caches must be flushed (step 2) after the CD flag is set to insure system memory
coherency. If the caches are not flushed, cache hits on reads will still occur and data
will be read from valid cache lines.
NOTES
Setting the CD flag in control register CR0 modifies the processor’s
caching behaviour as indicated in Table 10-5, but it does not force the
effective memory type for all physical memory to be UC nor does it
force strict memory ordering. To force the UC memory type and strict
memory ordering on all of physical memory, either the MTRRs must
all be programmed for the UC memory type or they must be disabled.
For the Pentium 4 and Intel Xeon processors, after the sequence of
steps given above has been executed, the cache lines containing the
code between the end of the WBINVD instruction and before the
MTRRS have actually been disabled may be retained in the cache
hierarchy. Here, to remove code from the cache completely, a second
WBINVD instruction must be executed after the MTRRs have been
disabled.
10.5.4 Disabling and Enabling the L3 Cache
Third-level cache disable flag (bit 6 of the IA32_MISC_ENABLE MSR) allows the L3
cache to be disabled and enabled, independently of the L1 and L2 caches. Prior to
using this control to disable or enable the L3 cache, software should disable and flush
all the processor caches, as described earlier in Section 10.5.3, “Preventing Caching,”
to prevent of loss of information stored in the L3 cache. After the L3 cache has been
disabled or enabled, caching for the whole processor can be restored.
10.5.5 Cache Management Instructions
The Intel 64 and IA-32 architectures provide several instructions for managing the
L1, L2, and L3 caches. The INVD, WBINVD, and WBINVD instructions are system
instructions that operate on the L1, L2, and L3 caches as a whole. The PREFETCHh