Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 10-23
MEMORY CACHE CONTROL
and CLFLUSH instructions and the non-temporal move instructions (MOVNTI,
MOVNTQ, MOVNTDQ, MOVNTPS, and MOVNTPD), which were introduced in
SSE/SSE2 extensions, offer more granular control over caching.
The INVD and WBINVD instructions are used to invalidate the contents of the L1, L2,
and L3 caches. The INVD instruction invalidates all internal cache entries, then
generates a special-function bus cycle that indicates that external caches also should
be invalidated. The INVD instruction should be used with care. It does not force a
write-back of modified cache lines; therefore, data stored in the caches and not
written back to system memory will be lost. Unless there is a specific requirement or
benefit to invalidating the caches without writing back the modified lines (such as,
during testing or fault recovery where cache coherency with main memory is not a
concern), software should use the WBINVD instruction.
The WBINVD instruction first writes back any modified lines in all the internal caches,
then invalidates the contents of both the L1, L2, and L3 caches. It ensures that cache
coherency with main memory is maintained regardless of the write policy in effect
(that is, write-through or write-back). Following this operation, the WBINVD instruc-
tion generates one (P6 family processors) or two (Pentium and Intel486 processors)
special-function bus cycles to indicate to external cache controllers that write-back of
modified data followed by invalidation of external caches should occur.
The PREFETCHh instructions allow a program to suggest to the processor that a
cache line from a specified location in system memory be prefetched into the cache
hierarchy (see Section 10.8, “Explicit Caching”).
The CLFLUSH instruction allow selected cache lines to be flushed from memory. This
instruction give a program the ability to explicitly free up cache space, when it is
known that cached section of system memory will not be accessed in the near future.
The non-temporal move instructions (MOVNTI, MOVNTQ, MOVNTDQ, MOVNTPS, and
MOVNTPD) allow data to be moved from the processor’s registers directly into
system memory without being also written into the L1, L2, and/or L3 caches. These
instructions can be used to prevent cache pollution when operating on data that is
going to be modified only once before being stored back into system memory. These
instructions operate on data in the general-purpose, MMX, and XMM registers.
10.5.6 L1 Data Cache Context Mode
L1 data cache context mode is a feature of Intel 64 and IA-32 processors that
support Hyper-Threading Technology. When CPUID.1:ECX[bit 10] = 1, the processor
supports setting L1 data cache context mode using the L1 data cache context mode
flag ( IA32_MISC_ENABLE[bit 24] ). Selectable modes are adaptive mode (default)
and shared mode.
The BIOS is responsible for configuring the L1 data cache context mode.