Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 10-27
MEMORY CACHE CONTROL
See Section 3.12, “Translation Lookaside Buffers (TLBs),” for additional information
about the TLBs.
10.10 STORE BUFFER
Intel 64 and IA-32 processors temporarily store each write (store) to memory in a
store buffer. The store buffer improves processor performance by allowing the
processor to continue executing instructions without having to wait until a write to
memory and/or to a cache is complete. It also allows writes to be delayed for more
efficient use of memory-access bus cycles.
In general, the existence of the store buffer is transparent to software, even in
systems that use multiple processors. The processor ensures that write operations
are always carried out in program order. It also insures that the contents of the store
buffer are always drained to memory in the following situations:
• When an exception or interrupt is generated.
• (P6 and more recent processor families only) When a serializing instruction is
executed.
• When an I/O instruction is executed.
• When a LOCK operation is performed.
• (P6 and more recent processor families only) When a BINIT operation is
performed.
• (Pentium III, and more recent processor families only) When using an SFENCE
instruction to order stores.
• (Pentium 4 and more recent processor families only) When using an MFENCE
instruction to order stores.
The discussion of write ordering in Section 7.2, “Memory Ordering,” gives a detailed
description of the operation of the store buffer.
10.11 MEMORY TYPE RANGE REGISTERS (MTRRS)
The following section pertains only to the P6 and more recent processor families.
The memory type range registers (MTRRs) provide a mechanism for associating the
memory types (see Section 10.3, “Methods of Caching Available”) with physical-
address ranges in system memory. They allow the processor to optimize operations
for different types of memory such as RAM, ROM, frame-buffer memory, and
memory-mapped I/O devices. They also simplify system hardware design by elimi-
nating the memory control pins used for this function on earlier IA-32 processors and
the external logic needed to drive them.
The MTRR mechanism allows up to 96 memory ranges to be defined in physical
memory, and it defines a set of model-specific registers (MSRs) for specifying the