Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

10-28 Vol. 3A
MEMORY CACHE CONTROL
type of memory that is contained in each range. Table 10-8 shows the memory types
that can be specified and their properties; Figure 10-3 shows the mapping of physical
memory with MTRRs. See Section 10.3, “Methods of Caching Available,” for a more
detailed description of each memory type.
Following a hardware reset, the P6 and more recent processor families disable all the
fixed and variable MTRRs, which in effect makes all of physical memory uncachable.
Initialization software should then set the MTRRs to a specific, system-defined
memory map. Typically, the BIOS (basic input/output system) software configures
the MTRRs. The operating system or executive is then free to modify the memory
map using the normal page-level cacheability attributes.
In a multiprocessor system using a processor in the P6 family or a more recent
family, each processor MUST use the identical MTRR memory map so that software
will have a consistent view of memory.
NOTE
In multiple processor systems, the operating system must maintain
MTRR consistency between all the processors in the system (that is,
all processors must use the same MTRR values). The P6 and more
recent processor families provide no hardware support for
maintaining this consistency.
Table 10-8. Memory Types That Can Be Encoded in MTRRs
Memory Type and Mnemonic Encoding in MTRR
Uncacheable (UC) 00H
Write Combining (WC) 01H
Reserved* 02H
Reserved* 03H
Write-through (WT) 04H
Write-protected (WP) 05H
Writeback (WB) 06H
Reserved* 7H through FFH
NOTE:
* Use of these encodings results in a general-protection exception (#GP).