Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 10-43
MEMORY CACHE CONTROL
10.11.8 MTRR Considerations in MP Systems
In MP (multiple-processor) systems, the operating systems must maintain MTRR
consistency between all the processors in the system. The Pentium 4, Intel Xeon, and
P6 family processors provide no hardware support to maintain this consistency. In
general, all processors must have the same MTRR values.
This requirement implies that when the operating system initializes an MP system, it
must load the MTRRs of the boot processor while the E flag in register MTRRdefType
is 0. The operating system then directs other processors to load their MTRRs with the
same memory map. After all the processors have loaded their MTRRs, the operating
system signals them to enable their MTRRs. Barrier synchronization is used to
prevent further memory accesses until all processors indicate that the MTRRs are
enabled. This synchronization is likely to be a shoot-down style algorithm, with
shared variables and interprocessor interrupts.
Any change to the value of the MTRRs in an MP system requires the operating system
to repeat the loading and enabling process to maintain consistency, using the
following procedure:
1. Broadcast to all processors to execute the following code sequence.
2. Disable interrupts.
3. Wait for all processors to reach this point.
4. Enter the no-fill cache mode. (Set the CD flag in control register CR0 to 1 and the
NW flag to 0.)
5. Flush all caches using the WBINVD instructions. Note on a processor that
supports self-snooping, CPUID feature flag bit 27, this step is unnecessary.
6. If the PGE flag is set in control register CR4, flush all TLBs by clearing that flag.
7. If the PGE flag is clear in control register CR4, flush all TLBs by executing a MOV
from control register CR3 to another register and then a MOV from that register
back to CR3.
8. Disable all range registers (by clearing the E flag in register MTRRdefType). If
only variable ranges are being modified, software may clear the valid bits for the
affected register pairs instead.
9. Update the MTRRs.
10. Enable all range registers (by setting the E flag in register MTRRdefType). If only
variable-range registers were modified and their individual valid bits were
cleared, then set the valid bits for the affected ranges instead.
11. Flush all caches and all TLBs a second time. (The TLB flush is required for Pentium
4, Intel Xeon, and P6 family processors. Executing the WBINVD instruction is not
needed when using Pentium 4, Intel Xeon, and P6 family processors, but it may
be needed in future systems.)
12. Enter the normal cache mode to re-enable caching. (Set the CD and NW flags in
control register CR0 to 0.)