Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

10-44 Vol. 3A
MEMORY CACHE CONTROL
13. Set PGE flag in control register CR4, if cleared in Step 6 (above).
14. Wait for all processors to reach this point.
15. Enable interrupts.
10.11.9 Large Page Size Considerations
The MTRRs provide memory typing for a limited number of regions that have a 4
KByte granularity (the same granularity as 4-KByte pages). The memory type for a
given page is cached in the processor’s TLBs. When using large pages (2 or 4
MBytes), a single page-table entry covers multiple 4-KByte granules, each with a
single memory type. Because the memory type for a large page is cached in the TLB,
the processor can behave in an undefined manner if a large page is mapped to a
region of memory that MTRRs have mapped with multiple memory types.
Undefined behavior can be avoided by insuring that all MTRR memory-type ranges
within a large page are of the same type. If a large page maps to a region of memory
containing different MTRR-defined memory types, the PCD and PWT flags in the
page-table entry should be set for the most conservative memory type for that
range. For example, a large page used for memory mapped I/O and regular memory
is mapped as UC memory. Alternatively, the operating system can map the region
using multiple 4-KByte pages each with its own memory type.
The requirement that all 4-KByte ranges in a large page are of the same memory
type implies that large pages with different memory types may suffer a performance
penalty, since they must be marked with the lowest common denominator memory
type.
The Pentium 4, Intel Xeon, and P6 family processors provide special support for
the physical memory range from 0 to 4 MBytes, which is potentially mapped by
both the fixed and variable MTRRs. This support is invoked when a Pentium 4, Intel
Xeon, or P6 family processor detects a large page overlapping the first 1 MByte of
this memory range with a memory type that conflicts with the fixed MTRRs. Here,
the processor maps the memory range as multiple 4-KByte pages within the TLB.
This operation insures correct behavior at the cost of performance. To avoid this
performance penalty, operating-system software should reserve the large page
option for regions of memory at addresses greater than or equal to 4 MBytes.
10.12 PAGE ATTRIBUTE TABLE (PAT)
The Page Attribute Table (PAT) extends the IA-32 architecture’s page-table format to
allow memory types to be assigned to regions of physical memory based on linear
address mappings. The PAT is a companion feature to the MTRRs; that is, the MTRRs
allow mapping of memory types to regions of the physical address space, where the
PAT allows mapping of memory types to pages within the linear address space. The
MTRRs are useful for statically describing memory types for physical ranges, and are
typically set up by the system BIOS. The PAT extends the functions of the PCD and