Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 10-45
MEMORY CACHE CONTROL
PWT bits in page tables to allow all five of the memory types that can be assigned
with the MTRRs (plus one additional memory type) to also be assigned dynamically
to pages of the linear address space.
The PAT was introduced to IA-32 architecture on the Pentium III processor. It is also
available in the Pentium 4 and Intel Xeon processors.
10.12.1 Detecting Support for the PAT Feature
An operating system or executive can detect the availability of the PAT by executing
the CPUID instruction with a value of 1 in the EAX register. Support for the PAT is indi-
cated by the PAT flag (bit 16 of the values returned to EDX register). If the PAT is
supported, the operating system or executive can use the IA32_CR_PAT MSR to
program the PAT. When memory types have been assigned to entries in the PAT, soft-
ware can then use of the PAT-index bit (PAT) in the page-table and page-directory
entries along with the PCD and PWT bits to assign memory types from the PAT to
individual pages.
Note that there is no separate flag or control bit in any of the control registers that
enables the PAT. The PAT is always enabled on all processors that support it, and the
table lookup always occurs whenever paging is enabled, in all paging modes.
10.12.2 IA32_CR_PAT MSR
The IA32_CR_PAT MSR is located at MSR address 277H (see to Appendix B, “Model-
Specific Registers (MSRs),” and this address will remain at the same address on
future IA-32 processors that support the PAT feature. Figure 10-7 shows the format
of the 64-bit IA32_CR_PAT MSR.
The IA32_CR_PAT MSR contains eight page attribute fields: PA0 through PA7. The
three low-order bits of each field are used to specify a memory type. The five high-
order bits of each field are reserved, and must be set to all 0s. Each of the eight
page attribute fields can contain any of the memory type encodings specified in
Table 10-10.
Figure 10-7. IA32_CR_PAT MSR
Note that for the P6 family processors, the IA32_CR_PAT MSR is named the PAT MSR.
312726242319181615111087320
Reserved PA3 Reserved PA2 Reserved PA1 Reserved PA0
63 59 58 56 55 51 50 48 47 43 42 40 39 35 34 32
Reserved PA7 Reserved PA6 Reserved PA5 Reserved PA4