Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 10-47
MEMORY CACHE CONTROL
10.12.4 Programming the PAT
Table 10-12 shows the default setting for each PAT entry following a power up or
reset of the processor. The setting remain unchanged following a soft reset (INIT
reset).
The values in all the entries of the PAT can be changed by writing to the
IA32_CR_PAT MSR using the WRMSR instruction. The IA32_CR_PAT MSR is read
and write accessible (use of the RDMSR and WRMSR instructions, respectively) to
software operating at a CPL of 0. Table 10-10 shows the allowable encoding of the
entries in the PAT. Attempting to write an undefined memory type encoding into the
PAT causes a general-protection (#GP) exception to be generated.
The operating system is responsible for insuring that changes to a PAT entry occur in
a manner that maintains the consistency of the processor caches and translation
lookaside buffers (TLB). This is accomplished by following the procedure as specified
in Section 10.11.8, “MTRR Considerations in MP Systems,” for changing the value of
an MTRR in a multiple processor system. It requires a specific sequence of operations
that includes flushing the processors caches and TLBs.
The PAT allows any memory type to be specified in the page tables, and therefore it
is possible to have a single physical page mapped to two or more different linear
addresses, each with different memory types. Intel does not support this practice
because it may lead to undefined operations that can result in a system failure. In
particular, a WC page must never be aliased to a cacheable page because WC writes
may not check the processor caches.
When remapping a page that was previously mapped as a cacheable memory type to
a WC page, an operating system can avoid this type of aliasing by doing the
following:
1. Remove the previous mapping to a cacheable memory type in the page tables;
that is, make them not present.
Table 10-12. Memory Type Setting of PAT Entries Following a Power-up or Reset
PAT Entry Memory Type Following Power-up or Reset
PAT0 WB
PAT1 WT
PAT2 UC-
PAT3 UC
PAT4 WB
PAT5 WT
PAT6 UC-
PAT7 UC