Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

10-48 Vol. 3A
MEMORY CACHE CONTROL
2. Flush the TLBs of processors that may have used the mapping, even specula-
tively.
3. Create a new mapping to the same physical address with a new memory type, for
instance, WC.
4. Flush the caches on all processors that may have used the mapping previously.
Note on processors that support self-snooping, CPUID feature flag bit 27, this
step is unnecessary.
Operating systems that use a page directory as a page table (to map large pages)
and enable page size extensions must carefully scrutinize the use of the PAT index bit
for the 4-KByte page-table entries. The PAT index bit for a page-table entry (bit 7)
corresponds to the page size bit in a page-directory entry. Therefore, the operating
system can only use PAT entries PA0 through PA3 when setting the caching type for
a page table that is also used as a page directory. If the operating system attempts
to use PAT entries PA4 through PA7 when using this memory as a page table, it effec-
tively sets the PS bit for the access to this memory as a page directory.
For compatibility with earlier IA-32 processors that do not support the PAT, care
should be taken in selecting the encodings for entries in the PAT (see Section
10.12.5, “PAT Compatibility with Earlier IA-32 Processors”).
10.12.5 PAT Compatibility with Earlier IA-32 Processors
For IA-32 processors that support the PAT, the IA32_CR_PAT MSR is always active.
That is, the PCD and PWT bits in page-table entries and in page-directory entries
(that point to pages) are always select a memory type for a page indirectly by
selecting an entry in the PAT. They never select the memory type for a page directly
as they do in earlier IA-32 processors that do not implement the PAT (see Table
10-6).
To allow compatibility for code written to run on earlier IA-32 processor that do not
support the PAT, the PAT mechanism has been designed to allow backward compati-
bility to earlier processors. This compatibility is provided through the ordering of the
PAT, PCD, and PWT bits in the 3-bit PAT entry index. For processors that do not imple-
ment the PAT, the PAT index bit (bit 7 in the page-table entries and bit 12 in the page-
directory entries) is reserved and set to 0. With the PAT bit reserved, only the first
four entries of the PAT can be selected with the PCD and PWT bits. At power-up or
reset (see Table 10-12), these first four entries are encoded to select the same
memory types as the PCD and PWT bits would normally select directly in an IA-32
processor that does not implement the PAT. So, if encodings of the first four entries
in the PAT are left unchanged following a power-up or reset, code written to run on
earlier IA-32 processors that do not implement the PAT will run correctly on IA-32
processors that do implement the PAT.