Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 12-1
CHAPTER 12
SYSTEM PROGRAMMING FOR STREAMING SIMD
INSTRUCTION SETS
This chapter describes features of the streaming SIMD extensions (SSE), streaming
SIMD extensions 2 (SSE2), streaming SIMD extensions 3 (SSE3), and Supplemental
SSE3 (SSSE3). These must be considered when designing or enhancing an operating
system to support Intel 64 and IA-32 processors.
The chapter covers enabling SSE/SSE2/SSE3/SSSE3 extensions, providing operating
system or executive support for the SSE/SSE2/SSE3/SSSE3 extensions, SIMD
floating-point exceptions, exception handling, and task (context) switching.
12.1 PROVIDING OPERATING SYSTEM SUPPORT FOR
SSE/SSE2/SSE3
/SSSE3 EXTENSIONS
To use SSE/SSE2/SSE3/SSSE3 extensions, the operating system or executive must
provide support for initializing the processor to use these extensions, for handling the
FXSAVE and FXRSTOR state saving instructions, and for handling SIMD floating-point
exceptions. The following sections provide guidelines for this support. Because
SSE/SSE2/SSE3/SSSE3 extensions share the same state and perform companion
operations, these guidelines apply to all four sets of extensions.
Chapter 11, “Programming with Streaming SIMD Extensions 2 (SSE2),” and Chapter
12, “Programming with SSE3 and Supplemental SSE3,” in the Intel® 64 and IA-32
Architectures Software Developer’s Manual, Volume 1, discuss support for
SSE/SSE2/SSE3/SSSE3 from an applications point of view program.
12.1.1 Adding Support to an Operating System for
SSE/SSE2/SSE3/SSSE3 Extensions
The following guidelines describe functions that an operating system or executive
must perform to support SSE/SSE2/SSE3/SSSE3 extensions:
1. Check that the processor supports the SSE/SSE2/SSE3/SSSE3 extensions.
2. Check that the processor supports the FXSAVE and FXRESTOR instructions.
3. Provide an initialization for the SSE, SSE2 SSE3, and SSSE3 states.
4. Provide support for the FXSAVE and FXRSTOR instructions.
5. Provide support (if necessary) in non-numeric exception handlers for exceptions
generated by the SSE and SSE2 instructions.
6. Provide an exception handler for the SIMD floating-point exception (#XF).