Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 12-3
SYSTEM PROGRAMMING FOR STREAMING SIMD INSTRUCTION SETS
NOTE
The OSFXSR and OSXMMEXCPT bits in control register CR4 must be
set by the operating system. The processor has no other way of
detecting operating-system support for the FXSAVE and FXRSTOR
instructions or for handling SIMD floating-point exceptions.
3. Clear CR0.EM[bit 2] = 0. This action disables emulation of the x87 FPU, which is
required when executing SSE/SSE2/SSE3/SSSE3 instructions (see Section 2.5,
“Control Registers”).
4. Set CR0.MP[bit 1] = 1. This setting is the required setting for Intel 64 and IA-32
processors that support the SSE/SSE2/SSE3/SSSE3 extensions (see Section
9.2.1, “Configuring the x87 FPU Environment”).
Table 12-1 and Table 12-2 show the actions of the processor when an
SSE/SSE2/SSE3/SSSE3 instruction is executed, depending on the:
• OSFXSR and OSXMMEXCPT flags in control register CR4
• SSE/SSE2/SSE3/SSSE3 feature flags returned by CPUID
• EM, MP, and TS flags in control register CR0
Table 12-1. Action Taken for Combinations of OSFXSR, OSXMMEXCPT, SSE, SSE2,
SSE3, EM, MP, and TS
1
CR4 CPUID CR0 Flags
OSFXSR OSXMMEXCPT
SSE,
SSE2,
SSE3 EM MP
2
TS Action
0X
3
XX1X#UD exception.
1X 0X1X#UD exception.
1X 111X#UD exception.
1 0 1 0 1 0 Execute instruction; #UD exception
if unmasked SIMD floating-point
exception is detected.
1 1 1 0 1 0 Execute instruction; #XF exception
if unmasked SIMD floating-point
exception is detected.
1X 1011#NM exception.
NOTES:
1. For execution of any SSE/SSE2/SSE3 instruction except the PAUSE, PREFETCHh, SFENCE,
LFENCE, MFENCE, MOVNTI, and CLFLUSH instructions.
2. For processors that support the MMX instructions, the MP flag should be set.
3. X — Don’t care.