Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

12-4 Vol. 3A

SYSTEM PROGRAMMING FOR STREAMING SIMD INSTRUCTION SETS

The SIMD floating-point exception mask bits (bits 7 through 12), the flush-to-zero

flag (bit 15), the denormals-are-zero flag (bit 6), and the rounding control field (bits

13 and 14) in the MXCSR register should be left in their default values of 0. This

permits the application to determine how these features are to be used.

12.1.5 Providing Non-Numeric Exception Handlers for Exceptions

Generated by the SSE/SSE2/SSE3/SSSE3 Instructions

SSE/SSE2/SSE3/SSSE3 instructions can generate the same type of memory access

exceptions (such as, page fault, segment not present, and limit violations) and other

non-numeric exceptions as other Intel 64 and IA-32 architecture instructions

generate.

Ordinarily, existing exception handlers can handle these and other non-numeric

exceptions without code modification. However, depending on the mechanisms used

in existing exception handlers, some modifications might need to be made.

The SSE/SSE2/SSE3/SSSE3 extensions can generate the non-numeric exceptions

listed below:

• Memory Access Exceptions:

— Invalid opcode (#UD).

— Stack-segment fault (#SS).

— General protection (#GP). Executing most SSE/SSE2/SSE3 instructions with

an unaligned 128-bit memory reference generates a general-protection

exception. (The MOVUPS and MOVUPD instructions allow unaligned a loads or

stores of 128-bit memory locations, without generating a general-protection

exception.) A 128-bit reference within the stack segment that is not aligned

to a 16-byte boundary will also generate a general-protection exception,

instead a stack-segment fault exception (#SS).

— Page fault (#PF).

Table 12-2. Action Taken for Combinations of OSFXSR, SSSE3, EM, and TS

CR4 CPUID CR0 Flags

OSFXSR SSSE3 EM TS Action

XX#UD exception.

10XX#UD exception.

111X#UD exception.

1101#NM exception.

NOTES:

1. X — Don’t care.