Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

12-6 Vol. 3A
SYSTEM PROGRAMMING FOR STREAMING SIMD INSTRUCTION SETS
12.1.6 Providing an Handler for the SIMD Floating-Point Exception
(#XF)
SSE/SSE2/SSE3/SSSE3 instructions do not generate numeric exceptions on packed
integer operations. They can generate the following numeric (SIMD floating-point)
exceptions on packed and scalar single-precision and double-precision floating-point
operations.
• Invalid operation (#I)
• Divide-by-zero (#Z)
• Denormal operand (#D)
• Numeric overflow (#O)
• Numeric underflow (#U)
• Inexact result (Precision) (#P)
These SIMD floating-point exceptions (with the exception of the denormal operand
exception) are defined in the IEEE Standard 754 for Binary Floating-Point Arithmetic
and represent the same conditions that cause x87 FPU floating-point error excep-
tions (#MF) to be generated for x87 FPU instructions.
Each of these exceptions can be masked, in which case the processor returns a
reasonable result to the destination operand without invoking an exception handler.
However, if any of these exceptions are left unmasked, detection of the exception
condition results in a SIMD floating-point exception (#XF) being generated. See
Chapter 5, “Interrupt 19—SIMD Floating-Point Exception (#XF).”
To handle unmasked SIMD floating-point exceptions, the operating system or execu-
tive must provide an exception handler. The section titled “SSE and SSE2 SIMD
Floating-Point Exceptions” in Chapter 11, “Programming with Streaming SIMD
Extensions 2 (SSE2),” of the Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 1, describes the SIMD floating-point exception classes and gives
suggestions for writing an exception handler to handle them.
To indicate that the operating system provides a handler for SIMD floating-point
exceptions (#XF), the OSXMMEXCPT flag (bit 10) must be set in control register CR0.
12.1.6.1 Numeric Error flag and IGNNE#
SSE/SSE2/SSE3 extensions ignore the NE flag in control register CR0 (that is, treats
it as if it were always set) and the IGNNE# pin. When an unmasked SIMD floating-
point exception is detected, it is always reported by generating a SIMD floating-point
exception (#XF).