Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 12-7
SYSTEM PROGRAMMING FOR STREAMING SIMD INSTRUCTION SETS
12.2 EMULATION OF SSE/SSE2/SSE3/SSSE3 EXTENSIONS
The Intel 64 and IA-32 architecture does not support emulation of the
SSE/SSE2/SSE3/SSSE3 instructions, as they do for x87 FPU instructions.
The EM flag in control register CR0 (provided to invoke emulation of x87 FPU instruc-
tions) cannot be used to invoke emulation of SSE/SSE2/SSE3/SSSE3 instructions. If
an SSE/SSE2/SSE3/SSSE3 instruction is executed when CR0.EM = 1, an invalid
opcode exception (#UD) is generated. See Table 12-1.
12.3 SAVING AND RESTORING THE
SSE/SSE2/SSE3/SSSE3 STATE
The SSE/SSE2/SSE3/SSSE3 state consists of the state of the XMM and MXCSR regis-
ters. The recommended method for saving and restoring this state follows:
Execute an FXSAVE instruction to save the state of the XMM and MXCSR registers
to memory.
Execute an FXRSTOR instruction to restore the state of the XMM and MXCSR
registers from the image saved in memory by the FXSAVE instruction.
This save and restore method is required for all operating systems. See Section 12.5,
“Designing OS Facilities for AUTOMATICALLY Saving x87 FPU, MMX, and
SSE/SSE2/SSE3/SSSE3 state on Task or Context Switches.
In some cases, applications can only save the XMM and MXCSR registers in the
following way:
Execute MOVDQ instructions to save the contents of each XMM registers to
memory.
Execute a STMXCSR instruction to save the state of the MXCSR register to
memory.
In some cases, applications can only restore the XMM and MXCSR registers in the
following way:
Execute MOVDQ instructions to read the saved contents of each XMM registers
from memory to XMM registers.
Execute a LDMXCSR instruction to restore the state of the MXCSR register from
memory.
12.4 SAVING THE SSE/SSE2/SSE3/SSSE3 STATE ON TASK
OR CONTEXT SWITCHES
When switching from one task or context to another, it is often necessary to save the
SSE/SSE2/SSE3/SSSE3 state. FXSAVE and FXRSTOR instructions provide a simple