Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 12-9
SYSTEM PROGRAMMING FOR STREAMING SIMD INSTRUCTION SETS
x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3 instruction needs to be executed in the
new task. (See Section 12.5.1., “Using the TS Flag to Control the Saving of the
x87 FPU, MMX, SSE, SSE2, SSE3 and SSSE3 State,” for more information.)
12.5.1. Using the TS Flag to Control the Saving of the
x87 FPU, MMX, SSE, SSE2, SSE3 and SSSE3 State
Saving the x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3 state using FXSAVE requires
processor overhead. If the new task does not access x87 FPU, MMX, XMM, and
MXCSR registers, avoid overhead by not automatically saving the state on a task
switch.
The TS flag in control register CR0 is provided to allow the operating system to delay
saving the x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3 state until an instruction that actu-
ally accesses this state is encountered in a new task. When the TS flag is set, the
processor monitors the instruction stream for an x87
FPU/MMX/SSE/SSE2/SSE3/SSSE3 instruction. When the processor detects one of
these instructions, it raises a device-not-available exception (#NM) prior to
executing the instruction. The device-not-available exception handler can then be
used to save the x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3 state for the previous task
(using an FXSAVE instruction) and load the x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3
state for the current task (using an FXRSTOR instruction). If the task never encoun-
ters an x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3 instruction, the device-not-available
exception will not be raised and a task state will not be saved unnecessarily.
The TS flag can be set either explicitly (by executing a MOV instruction to control
register CR0) or implicitly (using the IA-32 architecture’s native task switching mech-
anism). When the native task switching mechanism is used, the processor automati-
cally sets the TS flag on a task switch. After the device-not-available handler has
saved the x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3 state, it should execute the CLTS
instruction to clear the TS flag.
Figure 12-1 gives an example of an operating system that implements x87
FPU/MMX/SSE/SSE2/SSE3/SSSE3 state saving using the TS flag. In this example,
task A is the currently running task and task B is the new task. The operating system
maintains a save area for the x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3 state for each
task and defines a variable (x87_MMX_SSE_SSE2_SSE3_StateOwner) that indicates
the task that “owns” the state. In this example, task A is the current owner.
On a task switch, the operating system task switching code must execute the
following pseudo-code to set the TS flag according to the current owner of the x87
FPU/MMX/SSE/SSE2/SSE3/SSSE3 state. If the new task (task B in this example) is
not the current owner of this state, the TS flag is set to 1; otherwise, it is set to 0.