Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

12-10 Vol. 3A
SYSTEM PROGRAMMING FOR STREAMING SIMD INSTRUCTION SETS
IF Task_Being_Switched_To ≠ x87FPU_MMX_XMM_MXCSR_StateOwner
THEN
CR0.TS ← 1;
ELSE
CR0.TS ← 0;
FI;
If a new task attempts to access an x87 FPU, MMX, XMM, or MXCSR register while the
TS flag is set to 1, a device-not-available exception (#NM) is generated. The device-
not-available exception handler executes the following pseudo-code.
FXSAVE “To x87FPU/MMX/XMM/MXCSR State Save Area for Current
x87FPU_MMX_XMM_MXCSR_StateOwner”;
FXRSTOR “x87FPU/MMX/XMM/MXCSR State From Current Task’s
x87FPU/MMX/XMM/MXCSR State Save Area”;
x87FPU_MMX_XMM_MXCSR_StateOwner ← Current_Task;
CR0.TS ← 0;
This exception handler code performs the following tasks:
• Saves the x87 FPU, MMX, XMM, or MXCSR registers in the state save area for the
current owner of the x87 FPU/MMX/XMM/MXCSR state.
• Restores the x87 FPU, MMX, XMM, or MXCSR registers from the new task’s save
area for the x87 FPU/MMX/XMM/MXCSR state.
• Updates the current x87 FPU/MMX/XMM/MXCSR state owner to be the current
task.
• Clears the TS flag.
Figure 12-1. Example of Saving the x87 FPU, MMX, SSE, SSE2, SSE3, and SSSE3
State During an Operating-System Controlled Task Switch
Task A
Task B
Application
Operating System
Task A
Operating System
Task Switching Code
Device-Not-Available
Exception Handler
Owner of x87 FPU,
CR0.TS=1 and x87 FPU
MMX, SSEx
Instruction is encountered
MMX, XMM,
x87 FPU/MMX/
State Save Area
XMM/MXCSR
Task B
x87 FPU/MMX/
State Save Area
XMM/MXCSR
Saves Task A
x87 FPU/MMX/
XMM/MXCSR State
Loads Task B
x87 FPU/MMX/
XMM/MXCSR State
MXCSR State