Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 13-1
CHAPTER 13
POWER AND THERMAL MANAGEMENT
This chapter describes facilities of IA-32 architecture used for power management
and thermal monitoring.
13.1 ENHANCED INTEL SPEEDSTEP
®
TECHNOLOGY
Enhanced Intel SpeedStep
®
Technology was introduced in the Pentium M processor;
it is available in Pentium 4, Intel Xeon, Intel
®
Core™ Solo and Intel
®
Core™ Duo
processors. The technology manages processor power consumption using perfor-
mance state transitions. These states are defined as discrete operating points asso-
ciated with different frequencies.
Enhanced Intel SpeedStep Technology differs from previous generations of Intel
SpeedStep Technology in two ways:
• Centralization of the control mechanism and software interface in the processor
by using model-specific registers.
• Reduced hardware overhead; this permits more frequent performance state
transitions.
Previous generations of the Intel SpeedStep Technology require processors to be a
deep sleep state, holding off bus master transfers for the duration of a performance
state transition. Performance state transitions under the Enhanced Intel SpeedStep
Technology are discrete transitions to a new target frequency.
Support is indicated by CPUID, using ECX feature bit 07. Enhanced Intel SpeedStep
Technology is enabled by setting IA32_MISC_ENABLE MSR, bit 16. On reset, bit 16 of
IA32_MISC_ENABLE MSR is cleared.
13.1.1 Software Interface For Initiating Performance State
Transitions
State transitions are initiated by writing a 16-bit value to the IA32_PERF_CTL
register. If a transition is already in progress, transition to a new value will subse-
quently take effect.
Reads of IA32_PERF_CTL determine the last targeted operating point. The current
operating point can be read from IA32_PERF_STATUS. IA32_PERF_STATUS is
updated dynamically.
The 16-bit encoding that defines valid operating points is model-specific. Applications
and performance tools are not expected to use either IA32_PERF_CTL or
IA32_PERF_STATUS and should treat both as reserved. Performance monitoring