Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 13-5
POWER AND THERMAL MANAGEMENT
Executing MWAIT generates an exception on processors operating at a privilege level
where MONITOR/MWAIT are not supported.
NOTE
If MWAIT is used to enter a C-state (including sub C-state) that is
numerically higher than C1, a store to the address range armed by
MONITOR instruction will cause the processor to exit MWAIT if the
store was originated by other processor agents. A store from non-
processor agent may not cause the processor to exit MWAIT.
13.4 THERMAL MONITORING AND PROTECTION
The IA-32 architecture provides the following mechanisms for monitoring tempera-
ture and controlling thermal power:
1. The catastrophic shutdown detector forces processor execution to stop if
the processor’s core temperature rises above a preset limit.
2. Automatic thermal monitoring mechanism forces the processor to reduce
it’s power consumption in order to maintain a predetermined temperature limit.
3. The software controlled clock modulation mechanism permits operating
systems to implement power management policies that reduce power
consumption; this is in addition to the reduction offered by automatic thermal
monitoring mechanisms.
4. On-die digital thermal sensor and interrupt mechanisms permit the OS to
manage thermal conditions natively without relying on BIOS or other system
board components.
The first mechanism is not visible to software. The other three mechanisms are
visible to software using processor feature information returned by executing CPUID
with EAX = 1.
The second mechanism, automatic thermal monitoring, provides two modes of oper-
ation. One mode modulates the clock duty cycle; the second mode changes the
processor’s frequency. Both modes are used to control the core temperature of the
processor.
The third mechanism modulates the clock duty cycle of the processor. As shown in
Figure 13-2, the phrase ‘duty cycle’ does not refer to the actual duty cycle of the
clock signal. Instead it refers to the time period during which the clock signal is
allowed to drive the processor chip. By using the stop clock mechanism to control
how often the processor is clocked, processor power consumption can be modulated.