Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 13-11
POWER AND THERMAL MANAGEMENT
The IA32_CLOCK_MODULATION MSR contains the following flag and field used to
enable software-controlled clock modulation and to select the clock modulation duty
cycle:
• On-Demand Clock Modulation Enable, bit 4 — Enables on-demand software
controlled clock modulation when set; disables software-controlled clock
modulation when clear.
• On-Demand Clock Modulation Duty Cycle, bits 1 through 3 — Selects the
on-demand clock modulation duty cycle (see Table 13-1). This field is only active
when the on-demand clock modulation enable flag is set.
Note that the on-demand clock modulation mechanism (like the thermal monitor)
controls the processor’s stop-clock circuitry internally to modulate the clock signal.
The STPCLK# pin is not used in this mechanism.
The on-demand clock modulation mechanism can be used to control processor power
consumption. Power management software can write to the
IA32_CLOCK_MODULATION MSR to enable clock modulation and to select a modula-
tion duty cycle. If on-demand clock modulation and TM1 are both enabled and the
thermal status of the processor is hot (bit 0 of the IA32_THERM_STATUS MSR is set),
clock modulation at the duty cycle specified by TM1 takes precedence, regardless of
the setting of the on-demand clock modulation duty cycle.
For Hyper-Threading Technology enabled processors, the
IA32_CLOCK_MODULATION register is duplicated for each logical processor. In order
for the On-demand clock modulation feature to work properly, the feature must be
enabled on all the logical processors within a physical processor. If the programmed
duty cycle is not identical for all the logical processors, the processor clock will modu-
late to the highest duty cycle programmed.
For the P6 family processors, on-demand clock modulation was implemented
through the chipset, which controlled clock modulation through the processor’s
STPCLK# pin.
Table 13-1. On-Demand Clock Modulation Duty Cycle Field Encoding
Duty Cycle Field Encoding Duty Cycle
000B Reserved
001B 12.5% (Default)
010B 25.0%
011B 37.5%
100B 50.0%
101B 63.5%
110B 75%
111B 87.5%