Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

14-2 Vol. 3A
MACHINE-CHECK ARCHITECTURE
See Section 14.3.3, “Mapping of the Pentium
Processor Machine-Check Errors to the
Machine-Check Architecture,” and Section 14.8.3, “Pentium Processor Machine-
Check Exception Handling,” for information on compatibility between machine-check
code written to run on the Pentium processors and code written to run on P6 family
processors.
14.3 MACHINE-CHECK MSRS
Machine check MSRs in the Pentium 4, Intel Xeon, and P6 family processors consist
of a set of global control and status registers and several error-reporting register
banks. See Figure 14-1.
Each error-reporting bank is associated with a specific hardware unit (or group of
hardware units) in the processor. Use RDMSR and WRMSR to read and to write these
registers.
14.3.1 Machine-Check Global Control MSRs
The machine-check global control MSRs include the IA32_MCG_CAP,
IA32_MCG_STATUS, and IA32_MCG_CTL. See Appendix B, “Model-Specific Registers
(MSRs),” for the addresses of these registers.
Figure 14-1. Machine-Check MSRs
0
63
0
63
IA32_MCG_CAP MSR
IA32_MCG_STATUS MSR
Error-Reporting Bank Registers
0
63
0
63
IA32_MCi_CTL MSR
IA32_MCi_STATUS MSR
0
63
0
63
IA32_MCi_ADDR MSR
IA32_MCi_MISC MSR
Global Control MSRs
(One Set for Each Hardware Unit)
0
63
IA32_MCG_CTL MSR