Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 14-3
MACHINE-CHECK ARCHITECTURE
14.3.1.1 IA32_MCG_CAP MSR
The IA32_MCG_CAP MSR is a read-only register that provides information about the
machine-check architecture of the processor. Figure 14-2 shows the structure of the
register in Pentium 4, Intel Xeon, and P6 family processors.
Figure 14-2. IA32_MCG_CAP Register
Where:
• Count field, bits 7:0 — Indicates the number of hardware unit error-reporting
banks available in a particular processor implementation.
• MCG_CTL_P (control MSR present) flag, bit 8 — Indicates that the processor
implements the IA32_MCG_CTL MSR when set; this register is absent when clear.
• MCG_EXT_P (extended MSRs present) flag, bit 9 — Indicates that the
processor implements the extended machine-check state registers found starting
at MSR address 180H; these registers are absent when clear.
• MCG_TES_P (threshold-based error status present) flag, bit 11 —
Indicates (when set) that bits 56:53 of the IA32_MCi_STATUS MSR are part of
the architectural space. Bits 56:55 are reserved, and bits 54:53 are used to
report threshold-based error status. Note that when MCG_TES_P is not set, bits
56:53 of the IA32_MCi_STATUS MSR are model-specific.
• MCG_EXT_CNT, bits 23:16 — Indicates the number of extended machine-
check state registers present. This field is meaningful only when the MCG_EXT_P
flag is set.
The effect of writing to the IA32_MCG_CAP MSR is undefined.
0
Count
Reserved
7891011121516232463
MCG_EXT_CNT (23:16)
MCG_EXT_P (9)
MCG_CTL_P (8)
MCG_TES_P (11)