Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

14-4 Vol. 3A
MACHINE-CHECK ARCHITECTURE
14.3.1.2 IA32_MCG_STATUS MSR
The IA32_MCG_STATUS MSR describes the current state of the processor after a
machine-check exception has occurred (see Figure 14-3).
Where:
• RIPV (restart IP valid) flag, bit 0 — Indicates (when set) that program
execution can be restarted reliably at the instruction pointed to by the instruction
pointer pushed on the stack when the machine-check exception is generated.
When clear, the program cannot be reliably restarted at the pushed instruction
pointer.
• EIPV (error IP valid) flag, bit 1 — Indicates (when set) that the instruction
pointed to by the instruction pointer pushed onto the stack when the machine-
check exception is generated is directly associated with the error. When this flag
is cleared, the instruction pointed to may not be associated with the error.
• MCIP (machine check in progress) flag, bit 2 — Indicates (when set) that a
machine-check exception was generated. Software can set or clear this flag. The
occurrence of a second Machine-Check Event while MCIP is set will cause the
processor to enter a shutdown state. For information on processor behavior in
the shutdown state, please refer to the description in Chapter 5, “Interrupt and
Exception Handling”: “Interrupt 8—Double Fault Exception (#DF)”.
Bits 63:03 in IA32_MCG_STATUS are reserved.
14.3.1.3 IA32_MCG_CTL MSR
The IA32_MCG_CTL MSR is present if the capability flag MCG_CTL_P is set in the
IA32_MCG_CAP MSR.
IA32_MCG_CTL controls the reporting of machine-check exceptions. If present,
writing 1s to this register enables machine-check features and writing all 0s disables
machine-check features. All other values are undefined and/or implementation
specific.
Figure 14-3. IA32_MCG_STATUS Register
EIPV—Error IP valid flag
MCIP—Machine check in progress flag
63 0
Reserved
123
E
I
P
V
M
C
I
P
R
I
P
V
RIPV—Restart IP valid flag