Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1
Vol. 3A 14-5
MACHINE-CHECK ARCHITECTURE
14.3.2 Error-Reporting Register Banks
Each error-reporting register bank can contain the IA32_MCi_CTL,
IA32_MCi_STATUS, IA32_MCi_ADDR, and IA32_MCi_MISC MSRs. The Pentium 4 and
Intel Xeon processors provide four or five banks; the P6 family processors provide
five banks. The first error-reporting register (IA32_MC0_CTL) always starts at
address 400H.
See Appendix B, “Model-Specific Registers (MSRs),” for addresses of the error-
reporting registers in the Pentium 4 and Intel Xeon processors; and for addresses of
the error-reporting registers P6 family processors.
14.3.2.1 IA32_MCi_CTL MSRs
The IA32_MCi_CTL MSR controls error reporting for errors produced by a particular
hardware unit (or group of hardware units). Each of the 64 flags (EEj) represents a
potential error. Setting an EEj flag enables reporting of the associated error and
clearing it disables reporting of the error. The processor does not write changes to
bits that are not implemented. Figure 14-4 shows the bit fields of IA32_MCi_CTL.
NOTE
For P6 family processors only: the operating system or executive
software must not modify the contents of the IA32_MC0_CTL MSR.
This MSR is internally aliased to the EBL_CR_POWERON MSR and
controls platform-specific error handling features. System specific
firmware (the BIOS) is responsible for the appropriate initialization of
the IA32_MC0_CTL MSR. P6 family processors only allow the writing
of all 1s or all 0s to the IA32_MCi_CTL MSR.
14.3.2.2 IA32_MCi_STATUS MSRS
Each IA32_MCi_STATUS MSR contains information related to a machine-check error
if its VAL (valid) flag is set (see Figure 14-5). Software is responsible for clearing
IA32_MCi_STATUS MSRs by explicitly writing 0s to them; writing 1s to them causes
a general-protection exception.
Figure 14-4. IA32_MCi_CTL Register
EEj—Error reporting enable flag
63
0
123
E
E
0
1
E
E
0
2
E
E
0
0
E
E
6
1
E
E
6
2
E
E
6
3
62 61
. . . . .
(where j is 00 through 63)