Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

14-6 Vol. 3A
MACHINE-CHECK ARCHITECTURE
NOTE
Figure 14-5 depicts the IA32_MCi_STATUS MSR when
IA32_MCG_CAP[11] = 1. When IA32_MCG_CAP[11] = 0, bits 56:53
are part of the “Other Information” field. The use of bits 54:53 for
threshold-based error reporting began with Core Duo processors,
and is currently used for cache memory. See Section 14.4,
“Enhanced Cache Error reporting,” for more information.
Figure 14-5. IA32_MCi_STATUS Register
Where:
• MCA (machine-check architecture) error code field, bits 15:0 — Specifies
the machine-check architecture-defined error code for the machine-check error
condition detected. The machine-check architecture-defined error codes are
guaranteed to be the same for all IA-32 processors that implement the machine-
check architecture. See Section 14.7., “Interpreting the MCA Error Codes,” and
Appendix E, “Interpreting Machine-Check Error Codes”, for information on
machine-check error codes.
0313263 62 61 60 59 58 57 56
Other information
53 5255 54
PCC – Processor context corrupt (57)
MISCV – MCi_MISC register valid (59)
ADDRV – MCi_ADDR register valid (58)
Reserved (56:55)*
Threshold-based error status (54:53)*
EN – Error enabled (60)
OVER – Error overflow (62)
VAL – MCi_STATUS register valid (63)
UC – Error Uncorrected (61)
* When IA32_MCG_CAP[11] (MCG_TES_P) is not set, these bits are model-specific (part of “Other Information”).
MCA Error Code
1516
MCA Error Code