Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 14-9
MACHINE-CHECK ARCHITECTURE
If a second event overwrites a previously posted event, the information (as guarded
by individual valid bits) in the MCi bank is entirely from the second event. Similarly,
if a first event is retained, all of the information previously posted for that event is
retained. In either case, the OVER bit (MCi_Status[62]) will be set to indicate an
overflow.
After software polls a posting and clears the register, the valid bit is no longer set and
therefore the meaning of the rest of the bits, including the yellow/green/00 status
field in bits 54:53, is undefined. The yellow/green indication will only be posted for
events associated with monitored structures – otherwise the unmonitored (00) code
will be posted in MCi_Status[54:53].
14.3.2.3 IA32_MCi_ADDR MSRs
The IA32_MCi_ADDR MSR contains the address of the code or data memory location
that produced the machine-check error if the ADDRV flag in the IA32_MCi_STATUS
register is set (see Section 14-6, “IA32_MCi_ADDR MSR”). The IA32_MCi_ADDR
register is either not implemented or contains no address if the ADDRV flag in the
IA32_MCi_STATUS register is clear. When not implemented in the processor, all reads
and writes to this MSR will cause a general protection exception.
The address returned is an offset into a segment, linear address, or physical address.
This depends on the error encountered. These registers can be cleared by explicitly
writing 0s to bits that are not reserved. Writing 1s to these registers will cause a
general-protection exception. See Figure 14-6.
Table 14-2. Overwrite Rules for Enabled Errors
First Event Second Event UC bit Color MCA Info
00/green 00/green 0 00/green second
00/green yellow 0 yellow second error
yellow 00/green 0 yellow first error
yellow yellow 0 yellow either
00/green/yellow UC 1 undefined second
UC 00/green/yellow 1 undefined first