Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

14-10 Vol. 3A

MACHINE-CHECK ARCHITECTURE

14.3.2.4 IA32_MCi_MISC MSRs

The IA32_MCi_MISC MSR contains additional information describing the machine-

check error if the MISCV flag in the IA32_MCi_STATUS register is set. The

IA32_MCi_MISC_MSR is either not implemented or does not contain additional infor-

mation if the MISCV flag in the IA32_MCi_STATUS register is clear.

When not implemented in the processor, all reads and writes to this MSR will cause a

general protection exception. When implemented in a processor, these registers can

be cleared by explicitly writing all 0s to them; writing 1s to them causes a general-

protection exception to be generated. This register is not implemented in any of the

error-reporting register banks for the P6 family processors.

14.3.2.5 IA32_MCG Extended Machine Check State MSRs

The Pentium 4 and Intel Xeon processors implement a variable number of extended

machine-check state MSRs. The MCG_EXT_P flag in the IA32_MCG_CAP MSR indi-

cates the presence of these extended registers, and the MCG_EXT_CNT field indi-

cates the number of these registers actually implemented. See Section 14.3.1.1,

“IA32_MCG_CAP MSR.” Also see Table 14-3.

Figure 14-6. IA32_MCi_ADDR MSR

Table 14-3. Extended Machine Check State MSRs

in Processors Without Support for Intel 64 Architecture

MSR Address Description

IA32_MCG_EAX 180H Contains state of the EAX register at the time of the

machine-check error.

IA32_MCG_EBX 181H Contains state of the EBX register at the time of the

machine-check error.

Address

63 0

Reserved

Address

63 0

Processor Without Support For Intel 64 Architecture

Processor With Support for Intel 64 Architecture

* Useful bits in this field depend on the address methodology in use when the

the register state is saved.