Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 14-13
MACHINE-CHECK ARCHITECTURE
and the R/EIP in these extended machine-check state MSRs. This information can be
used by a debugger to analyze the error.
These registers are read/write to zero registers. This means software can read them;
but if software writes to them, only all zeros is allowed. If software attempts to write
a non-zero value into one of these registers, a general-protection (#GP) exception is
generated. These registers are cleared on a hardware reset (power-up or RESET),
but maintain their contents following a soft reset (INIT reset).
14.3.3 Mapping of the Pentium Processor Machine-Check Errors
to the Machine-Check Architecture
The Pentium processor reports machine-check errors using two registers:
P5_MC_TYPE and P5_MC_ADDR. The Pentium 4, Intel Xeon, and P6 family proces-
sors map these registers to the IA32_MCi_STATUS and IA32_MCi_ADDR in the error-
reporting register bank. This bank reports on the same type of external bus errors
reported in P5_MC_TYPE and P5_MC_ADDR.
The information in these registers can then be accessed in two ways:
• By reading the IA32_MCi_STATUS and IA32_MCi_ADDR registers as part of a
general machine-check exception handler written for Pentium 4 and P6 family
processors.
• By reading the P5_MC_TYPE and P5_MC_ADDR registers using the RDMSR
instruction.
The second capability permits a machine-check exception handler written to run on a
Pentium processor to be run on a Pentium 4, Intel Xeon, or P6 family processor. There
is a limitation in that information returned by the Pentium 4, Intel Xeon, and P6
family processors is encoded differently than information returned by the Pentium
processor. To run a Pentium processor machine-check exception handler on a
Pentium 4, Intel Xeon, or P6 family processor; the handler must be written to inter-
pret P5_MC_TYPE encodings correctly.
14.4 ENHANCED CACHE ERROR REPORTING
Starting with Core Duo processors, cache error reporting was enhanced. In earlier
Intel processors, cache status was based on the number of correction events that
occurred in a cache. In the new paradigm, called “threshold-based error status”,
cache status is based on the number of lines (ECC blocks) in a cache that incur
repeated corrections. The threshold is chosen by Intel, based on various factors. If a
processor supports threshold-based error status, it sets IA32_MCG_CAP[11]
(MCG_TES_P) to 1; if not, to 0.
A processor that supports enhanced cache error reporting contains hardware that
tracks the operating status of certain caches and provides an indicator of their
“health”. The hardware reports a “green” status when the number of lines that incur