Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

14-14 Vol. 3A
MACHINE-CHECK ARCHITECTURE
repeated corrections is at or below a pre-defined threshold, and a “yellow” status
when the number of affected lines exceeds the threshold. Yellow status means that
the cache reporting the event is operating correctly, but you should schedule the
system for servicing within a few weeks.
Intel recommends that you rely on this mechanism for structures supported by
threshold-base error reporting.
The CPU/system/platform response to a yellow event should be less severe than its
response to an uncorrected error. An uncorrected error means that a serious error
has actually occurred, whereas the yellow condition is a warning that the number of
affected lines has exceeded the threshold but is not, in itself, a serious event: the
error was corrected and system state was not compromised.
The green/yellow status indicator is not a foolproof early warning for an uncorrected
error resulting from the failure of two bits in the same ECC block. Such a failure can
occur and cause an uncorrected error before the yellow threshold is reached.
However, the chance of an uncorrected error increases as the number of affected
lines increases.
14.5 MACHINE-CHECK AVAILABILITY
The machine-check architecture and machine-check exception (#MC) are model-
specific features. Software can execute the CPUID instruction to determine whether
a processor implements these features. Following the execution of the CPUID
instruction, the settings of the MCA flag (bit 14) and MCE flag (bit 7) in EDX indicate
whether the processor implements the machine-check architecture and machine-
check exception.
14.6 MACHINE-CHECK INITIALIZATION
To use the processors machine-check architecture, software must initialize the
processor to activate the machine-check exception and the error-reporting mecha-
nism.
Example 14-1 gives pseudocode for performing this initialization. This pseudocode
checks for the existence of the machine-check architecture and exception; it then
enables machine-check exception and the error-reporting register banks. The
pseudocode shown is compatible with the Pentium 4, Intel Xeon, P6 family, and
Pentium processors.
Following power up or power cycling, IA32_MCi_STATUS registers are not guaran-
teed to have valid data until after they are initially cleared to zero by software (as
shown in the initialization pseudocode in Example 14-1). In addition, when using P6
family processors, software must set MCi_STATUS registers to zero when doing a
soft-reset.