Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

14-16 Vol. 3A
MACHINE-CHECK ARCHITECTURE
DO
IA32_MCi_STATUS
← 0;
OD
ELSE
FOR error-reporting banks (0 through MAX_BANK_NUMBER)
DO
(Optional for BIOS and OS) Log valid errors
(OS only) IA32_MCi_STATUS
← 0;
OD
FI
FI
FI
Setup the Machine Check Exception (#MC) handler for vector 18 in IDT
Set the MCE bit (bit 6) in CR4 register to enable Machine-Check Exceptions
FI
14.7. INTERPRETING THE MCA ERROR CODES
When the processor detects a machine-check error condition, it writes a 16-bit error
code to the MCA error code field of one of the IA32_MCi_STATUS registers and sets
the VAL (valid) flag in that register. The processor may also write a 16-bit model-
specific error code in the IA32_MCi_STATUS register depending on the implementa-
tion of the machine-check architecture of the processor.
The MCA error codes are architecturally defined for IA-32 processors. However, the
specific IA32_MCi_STATUS register that a code is ‘written to’ is model specific. To
determine the cause of a machine-check exception, the machine-check exception
handler must read the VAL flag for each IA32_MCi_STATUS register. If the flag is set,
the machine check-exception handler must then read the MCA error code field of the
register. It is the encoding of the MCA error code field [15:0] that determines the
type of error being reported and not the register bank reporting it.
There are two types of MCA error codes: simple error codes and compound error
codes.
14.7.1 Simple Error Codes
Table 14-5 shows the simple error codes. These unique codes indicate global error
information.