Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 14-17
MACHINE-CHECK ARCHITECTURE
14.7.2 Compound Error Codes
Compound error codes describe errors related to the TLBs, memory, caches, bus and
interconnect logic, and internal timer. A set of sub-fields is common to all of
compound errors. These sub-fields describe the type of access, level in the memory
hierarchy, and type of request. Table 14-6 shows the general form of the compound
error codes.
Table 14-5. IA32_MCi_Status [15:0] Simple Error Code Encoding
Error Code Binary Encoding Meaning
No Error 0000 0000 0000 0000 No error has been reported to this bank of
error-reporting registers.
Unclassified 0000 0000 0000 0001 This error has not been classified into the
MCA error classes.
Microcode ROM Parity
Error
0000 0000 0000 0010 Parity error in internal microcode ROM
External Error 0000 0000 0000 0011 The BINIT# from another processor caused
this processor to enter machine check.
1
FRC Error 0000 0000 0000 0100 FRC (functional redundancy check)
master/slave error
Internal Timer Error 0000 0100 0000 0000 Internal timer error.
Internal Unclassified 0000 01xx xxxx xxxx Internal unclassified errors.
2
NOTES:
1. BINIT# assertion will cause a machine check exception if the processor (or any processor on the
same external bus) has BINIT# observation enabled during power-on configuration (hardware
strapping) and if machine check exceptions are enabled (by setting CR4.MCE = 1).
2. At least one X must equal one. Internal unclassified errors have not been classified. This is
because no additional information is included in the machine check register.
Table 14-6. IA32_MCi_Status [15:0] Compound Error Code Encoding
Type Form Interpretation
Generic Memory
Hierarchy
000F 0000 0000 11LL Generic memory hierarchy error
TLB Errors 000F 0000 0001 TTLL {TT}TLB{LL}_ERR
Memory Hierarchy Errors 000F 0001 RRRR TTLL {TT}CACHE{LL}_{RRRR}_ERR
Bus and Interconnect
Errors
000F 1PPT RRRR IILL BUS{LL}_{PP}_{RRRR}_{II}_{T}_ERR