Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

14-18 Vol. 3A
MACHINE-CHECK ARCHITECTURE
The “Interpretation” column in the table indicates the name of a compound error. The
name is constructed by substituting mnemonics for the sub-field names given within
curly braces. For example, the error code ICACHEL1_RD_ERR is constructed from the
form:
{TT}CACHE{LL}_{RRRR}_ERR,
where {TT} is replaced by I, {LL} is replaced by L1, and {RRRR} is replaced by RD.
For more information on the “Form” and “Interpretation” columns, see Sections
Section 14.7.2.1, “Correction Report Filtering (F) Bit” through Section 14.7.2.5, “Bus
and Interconnect Errors”.
14.7.2.1 Correction Report Filtering (F) Bit
Starting with Core Duo processors, bit 12 in the “Form” column in Table 14-6 is used
to indicate that a particular posting to a log may be the last posting for corrections in
that line/entry, at least for some time:
• 0 in bit 12 indicates “normal” filtering (original P6/Pentium4/Xeon processor
meaning).
• 1 in bit 12 indicates “corrected” filtering (filtering is activated for the line/entry in
the posting). Filtering means that some or all of the subsequent corrections to
this entry (in this structure) will not be posted. The enhanced error reporting
introduced with the Core Duo processors is based on tracking the lines affected
by repeated corrections (see Section 14.4, “Enhanced Cache Error reporting”).
Only the first few correction events for a line are posted; subsequent redundant
correction events to the same line are not posted. Uncorrected events are always
posted.
The behavior of error filtering after crossing the yellow threshold is model-specific.
14.7.2.2 Transaction Type (TT) Sub-Field
The 2-bit TT sub-field (Table 14-7) indicates the type of transaction (data, instruc-
tion, or generic). The sub-field applies to the TLB, cache, and interconnect error
conditions. Note that interconnect error conditions are primarily associated with P6
family and Pentium processors, which utilize an external APIC bus separate from the
system bus. The generic type is reported when the processor cannot determine the
transaction type.
Table 14-7. Encoding for TT (Transaction Type) Sub-Field
Transaction Type Mnemonic Binary Encoding
Instruction I 00
Data D 01
Generic G 10