Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 14-19
MACHINE-CHECK ARCHITECTURE
14.7.2.3 Level (LL) Sub-Field
The 2-bit LL sub-field (see Table 14-8) indicates the level in the memory hierarchy
where the error occurred (level 0, level 1, level 2, or generic). The LL sub-field also
applies to the TLB, cache, and interconnect error conditions. The Pentium 4, Intel
Xeon, and P6 family processors support two levels in the cache hierarchy and one
level in the TLBs. Again, the generic type is reported when the processor cannot
determine the hierarchy level.
14.7.2.4 Request (RRRR) Sub-Field
The 4-bit RRRR sub-field (see Table 14-9) indicates the type of action associated with
the error. Actions include read and write operations, prefetches, cache evictions, and
snoops. Generic error is returned when the type of error cannot be determined.
Generic read and generic write are returned when the processor cannot determine
the type of instruction or data request that caused the error. Eviction and snoop
requests apply only to the caches. All of the other requests apply to TLBs, caches and
interconnects.
Table 14-8. Level Encoding for LL (Memory Hierarchy Level) Sub-Field
Hierarchy Level Mnemonic Binary Encoding
Level 0 L0 00
Level 1 L1 01
Level 2 L2 10
Generic LG 11
Table 14-9. Encoding of Request (RRRR) Sub-Field
Request Type Mnemonic Binary Encoding
Generic Error ERR 0000
Generic Read RD 0001
Generic Write WR 0010
Data Read DRD 0011
Data Write DWR 0100
Instruction Fetch IRD 0101
Prefetch PREFETCH 0110
Eviction EVICT 0111
Snoop SNOOP 1000