Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 15-19
8086 EMULATION
8086-mode task, can use the same code sequences for saving and restoring the
registers for any task. Clearing these registers before execution of the IRET
instruction does not cause a trap in the interrupt handler. Interrupt procedures
that expect values in the segment registers or that return values in the segment
registers must use the register images saved on the stack for privilege level 0.
4. Clears VM, NT, RF and TF flags (in the EFLAGS register). If the gate is an interrupt
gate, clears the IF flag.
5. Begins executing the selected interrupt or exception handler.
If the trap or interrupt gate references a procedure in a conforming segment or in a
segment at a privilege level other than 0, the processor generates a general-protec-
tion exception (#GP). Here, the error code is the segment selector of the code
segment to which a call was attempted.
Interrupt and exception handlers can examine the VM flag on the stack to determine
if the interrupted procedure was running in virtual-8086 mode. If so, the interrupt or
exception can be handled in one of three ways:
• The protected-mode interrupt or exception handler that was called can handle
the interrupt or exception.
Figure 15-4. Privilege Level 0 Stack After Interrupt or
Exception in Virtual-8086 Mode
Unused
Old GS
Old ESP
With Error Code
ESP from
Old FS
Old DS
Old ES
Old SS
Old EFLAGS
Old CS
Old EIP
Error Code
New ESP
TSS
Unused
Old GS
Old ESP
Without Error Code
ESP from
Old FS
Old DS
Old ES
Old SS
Old EFLAGS
Old CS
Old EIP
New ESP
TSS