Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 17-5
ARCHITECTURE COMPATIBILITY
17.11 SPECIFIC FEATURES OF DUAL-CORE PROCESSOR
Dual-core processors may have some processor-specific features. Use CPUID feature
flags to detect the availability features. Note the following:
• CPUID Brand String — On Pentium processor Extreme Edition, the process will
report the correct brand string only after the correct microcode updates are
loaded.
• Enhanced Intel SpeedStep Technology — This feature is supported in
Pentium D processor but not in Pentium processor Extreme Edition.
17.12 NEW INSTRUCTIONS IN THE PENTIUM AND LATER
IA-32 PROCESSORS
Table 17-1 identifies the instructions introduced into the IA-32 in the Pentium
processor and later IA-32 processors.
17.12.1 Instructions Added Prior to the Pentium Processor
The following instructions were added in the Intel486 processor:
• BSWAP (byte swap) instruction.
• XADD (exchange and add) instruction.
• CMPXCHG (compare and exchange) instruction.
• ΙNVD (invalidate cache) instruction.
• WBINVD (write-back and invalidate cache) instruction.
• INVLPG (invalidate TLB entry) instruction.
Table 17-1. New Instruction in the Pentium Processor and
Later IA-32 Processors
Instruction CPUID Identification Bits Introduced In
CMOVcc (conditional move) EDX, Bit 15 Pentium Pro processor
FCMOVcc (floating-point conditional
move)
EDX, Bits 0 and 15
FCOMI (floating-point compare and set
EFLAGS)
EDX, Bits 0 and 15
RDPMC (read performance monitoring
counters)
EAX, Bits 8-11, set to 6H;
see Note 1
UD2 (undefined) EAX, Bits 8-11, set to 6H