Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

17-6 Vol. 3A
ARCHITECTURE COMPATIBILITY
The following instructions were added in the Intel386 processor:
• LSS, LFS, and LGS (load SS, FS, and GS registers).
• Long-displacement conditional jumps.
• Single-bit instructions.
• Bit scan instructions.
• Double-shift instructions.
• Byte set on condition instruction.
• Move with sign/zero extension.
• Generalized multiply instruction.
• MOV to and from control registers.
• MOV to and from test registers (now obsolete).
• MOV to and from debug registers.
• RSM (resume from SMM). This instruction was introduced in the Intel386 SL and
Intel486 SL processors.
The following instructions were added in the Intel 387 math coprocessor:
• FPREM1.
• FUCOM, FUCOMP, and FUCOMPP.
CMPXCHG8B (compare and exchange 8
bytes)
EDX, Bit 8 Pentium processor
CPUID (CPU identification) None; see Note 2
RDTSC (read time-stamp counter) EDX, Bit 4
RDMSR (read model-specific register) EDX, Bit 5
WRMSR (write model-specific register) EDX, Bit 5
MMX Instructions EDX, Bit 23
NOTES:
1. The RDPMC instruction was introduced in the P6 family of processors and added to later model
Pentium processors. This instruction is model specific in nature and not architectural.
2. The CPUID instruction is available in all Pentium and P6 family processors and in later models of
the Intel486 processors. The ability to set and clear the ID flag (bit 21) in the EFLAGS register
indicates the availability of the CPUID instruction.
Table 17-1. New Instruction in the Pentium Processor and
Later IA-32 Processors (Contd.)
Instruction CPUID Identification Bits Introduced In