Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

17-8 Vol. 3A
ARCHITECTURE COMPATIBILITY
family or Pentium processor. The CPUID instruction can then be used to
determine which processor.
• Bits 19 (the VIF flag) and 20 (the VIP flag) will always be zero on processors that
do not support virtual mode extensions, which includes all 32-bit processors prior
to the Pentium processor.
See Chapter 14, “Processor Identification and Feature Determination,” in the Intel®
64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for more infor-
mation on identifying processors.
17.16 STACK OPERATIONS
This section identifies the differences in stack implementation between the various
IA-32 processors.
17.16.1 PUSH SP
The P6 family, Pentium, Intel486, Intel386, and Intel 286 processors push a different
value on the stack for a PUSH SP instruction than the 8086 processor. The 32-bit
processors push the value of the SP register before it is decremented as part of the
push operation; the 8086 processor pushes the value of the SP register after it is
decremented. If the value pushed is important, replace PUSH SP instructions with the
following three instructions:
PUSH BP
MOV BP, SP
XCHG BP, [BP]
This code functions as the 8086 processor PUSH SP instruction on the P6 family,
Pentium, Intel486, Intel386, and Intel 286 processors.
17.16.2 EFLAGS Pushed on the Stack
The setting of the stored values of bits 12 through 15 (which includes the IOPL field
and the NT flag) in the EFLAGS register by the PUSHF instruction, by interrupts, and
by exceptions is different with the 32-bit IA-32 processors than with the 8086 and
Intel 286 processors. The differences are as follows:
• 8086 processor—bits 12 through 15 are always set.
• Intel 286 processor—bits 12 through 15 are always cleared in real-address mode.
• 32-bit processors in real-address mode—bit 15 (reserved) is always cleared, and
bits 12 through 14 have the last value loaded into them.